12 bit 30 MSPS逐次比较型ADC的测试
Testing of a 12 bit 30 MSPS SAR ADC
查看参考文献11篇
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文摘
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针对物理实验读出的需求设计了一款低功耗12 bit 30 MSPS逐次比较型模数变换器(Analog-to-Digital Converter, ADC)芯片,为评估其性能指标参数,需进行系统的测试.在本研究工作中构建了测试系统,然后按照IEEE标准进行了系统的测试和分析.测试结果表明,输入信号在基带范围内ADC有效位(Effective Number Of Bit, ENOB)约为9 bit,达到了本版本芯片的设计指标.同时,综合分析静态性能与动态性能测试结果,可以通过优化逐次比较型ADC中电容阵列电容失配参数,进一步提升ADC的非线性指标,为下一版芯片的改进设计提供了参考依据. |
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其他语种文摘
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Aiming at the requirement of readout electronics in physics experiments, a 12 bit 30 MSPS successiveapproximation- register (SAR) analog-to-digital converter (ADC) with low power consumption has been designed. To evaluate the performance of this ASIC, we conducted a series of tests. We set up a test system, and we tested the ADC according to IEEE std 1241-2010. The test results indicate that the effective number of bit (ENOB) of the ADC is around 9 bits when the input signal is in the first Nyquist zone, which has met the design requirements. According to the results of dynamic and static tests of this ADC, we found that the non-linearity performance of this ASIC can be further enhanced by improving the mismatching among the capacitor array, and this provides important information for the design of the second version of this ADC. |
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来源
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原子核物理评论
,2018,35(1):46-52 【核心库】
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DOI
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10.11804/NuclPhysRev.35.01.046
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关键词
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模数转换器
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逐次比较
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动态性能测试
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静态性能测试
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地址
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1.
中国科学技术大学, 核探测与核电子学国家重点实验室, 合肥, 230026
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中国科学技术大学近代物理系, 合肥, 230026
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语种
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中文 |
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文献类型
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研究性论文 |
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ISSN
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1007-4627 |
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学科
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原子能技术 |
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基金
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国家自然科学基金资助项目
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中国科学院知识创新工程重要方向项目
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文献收藏号
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CSCD:6230460
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