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一种基于并行处理器的快速车道线检测系统及FPGA实现
A Fast Traffic Lane Detection System Based on Parallel Processors and FPGA Implementation
查看参考文献8篇
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文摘
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该文提出了一种并行的快速车道线检测系统.该系统包含一个32×32的处理器单元(PE)阵列和双RISC子系统.PE阵列实现车道线图像像素级并行预处理,获取图像边缘特征,双RISC核子系统根据边缘特征实现两条车道线直线参数的并行检测,从而使得检测过程的每一步都是并行进行,显著提高检测速率.该系统用FPGA实现.实验结果表明本系统具有良好的鲁棒性且可达到每秒50帧的检测速率,满足了车道偏离预警系统实时性要求,具备重要的应用价值 |
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其他语种文摘
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This paper proposes a parallel fast traffic lane detection system. The system consists of a 32×32 Processing Elements (PE) array and a dual RISC core subsystem. The PE array performs pixel-parallel image preprocessing and outputs edge features, the dual RISC core subsystem performs two lanes parameters detection in parallel based on edge features. In this way, every step in the detection process is in parallel and the detection rate is rapidly increased. The system is implemented with FPGA. The experiment shows that it has good robustness and can reach up to 50 fps. This meets the demand of real-time for lane departure warning system and makes an important sense for practical application |
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来源
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电子与信息学报
,2010,32(12):2901-2906 【核心库】
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DOI
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10.3724/sp.j.1146.2010.00111
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关键词
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图像处理
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车道线检测
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并行
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FPGA
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精简指令集计算机(RISC)
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地址
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中国科学院半导体研究所, 北京, 100083
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语种
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中文 |
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文献类型
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研究性论文 |
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ISSN
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1009-5896 |
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学科
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电子技术、通信技术;自动化技术、计算机技术 |
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基金
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国家自然科学基金
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文献收藏号
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CSCD:4086148
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参考文献 共
8
共1页
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1.
余天洪.
基于机器视觉的车道偏离预警系统的研究.[博士论文],2006
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被引
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汽车工程,2005,27(4):463-464
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被引
15
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3.
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被引
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被引
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5.
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被引
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6.
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Sensors,2009,9(8):5933-5951
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被引
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7.
田炳香. 高速公路车道线检测与跟踪算法研究.
现代电子技术,2008,9(31):180-183
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被引
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8.
Huang Pei-yung. A portable vision-based real-time lane departure warning system based on embedded calculating technique.
Vehicular Technology Conference,Australia May 7-10,2006:2982-2986
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被引
1
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