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基于制作离散性对策的高性能CMOS DAC
High-Performance CMOS D/A Converter Based on Offsetting Variations in Processing
查看参考文献10篇
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文摘
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基于CMOS器件的离散性机理及误差消除对策，研究了高速、高精度嵌入式CMOS数/模转换器（DAC）IP核的设计与实现。采用行、列独立译码的二次中心对称电流源矩阵结构，优化了电流源开关电路结构与开关次序；利用Cadence的Skill语言独立开发电流源矩阵的版图排序和布线方法。在0.6μm N阱CMOS工艺平台下，12-bitDAC的微分线性误差和积分线性误差分别为1LSB和1.5LSB，在采样率为150MHz、工作电源为3.3V时的平均耗为140mW。流片一次成功，主要性能指标满足设计要求。 |
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其他语种文摘
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The design and implementation of high-speed,high-accuracy embedded CMOS D/A converter(DAC) IP core are presented,which is based on the principle of variations of CMOS devices and the method to offset the errors. It is implemented in a double centroid current-steering architecture with the rows and the columns decoded separately,and the current source switching circuit and the switching sequence are optimized. Cadence Skill language is used to develop the sorting and routing methods of the current source matrix in layout. The 12-bit DAC was integrated in a standard 0. 6μm N-well CMOS process and the anticipated integral and differential nonlinearity performances are 1LSB and 1. 5LSB, respectively. With a supply of 3. 3V and sampling rate of 150MHz,the average power consumption is 140mW. The DAC is successfully fabricated and the main specifications meet the expectations. |
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来源
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半导体学报
,2003,24(11):1211-1216 【核心库】
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关键词
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D/A转换器
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CMOS混合集成电路
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制作工艺离散性
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中心对称
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Skill语言
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地址
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中国科学院半导体研究所, 北京, 100083
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语种
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中文 |
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文献类型
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研究性论文 |
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ISSN
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0253-4177 |
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学科
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电子技术、通信技术 |
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基金
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国家863计划
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文献收藏号
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CSCD:1236143
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参考文献 共
10
共1页
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